features ? floating channel designed for bootstrap operation fully operational up to +200v tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10v to 20v ? independent low and high side channels ? input logichin/lin active high ? undervoltage lockout for both channels ? 3.3v and 5v input logic compatible ? cmos schmitt-triggered inputs with pull-down ? matched propagation delay for both channels packages high and low side driver product summary v offset 200v max. i o +/- 1.0a /1.0a typ. v out 10 - 20v t on/off 80 & 60 ns typ. delay matching 20 ns max. IR2011( s ) www.irf.com 1 typical connection (refer to lead assignments for correct configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. data sheet no.pd60217 applications ? audio class d amplifiers ? high power dc-dc smps converters ? other high frequency applications advance data description the IR2011 is a high power, high speed power mosfet driver with independent high and low side referenced output channels, ideal for audio class d and dc-dc converter applications. logic inputs are compatible with standard cmos or lsttl output, down to 3.0v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet in the high side configuration which operates up to 200 volts. propri- etary hvic and latch immune cmos technologies enable ruggedized monolithic con- struction. 8-lead soic 8-lead pdip 200v to load v cc com lin hin v s v b ho hin com v cc lin lo 1 8 4 5
2 www.irf.com IR2011( s ) advance data absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 250 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc +0.3 v in logic input voltage (hin & lin) com -0.3 v cc +0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25 c (8-lead dip) ? 1.0 (8-lead soic) ? 0.625 r thja thermal resistance, junction to ambient (8-l ead dip) ? 125 (8-lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c/w w v c note 1: logic operational for v s of -4 to +200v. logic state held for v s of -4v to -v bs . symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 200 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (hin & lin) com 5.5 t a ambient temperature -40 125 c recommended operating conditions for proper operation the device should be used within the recommended conditions. the v s and com offset ratings are tested with all supplies biased at 15v differential. v
www.irf.com 3 IR2011( s ) advance data symbol definition min. typ. max. units test conditions v ih logic ?1? input voltage 2.2 ? ? v il logic ?0? input voltage ? ? 1.2 v oh high level output voltage, v bias - v o ? ? 1.0 i o = 0a v ol low level output voltage, v o ? ? 0.1 i o = 0a i lk offset supply leakage current ? ? 50 v b =v s = 200v i qbs quiescent v bs supply current ? 70 210 v in = 0v or 3.3v i qcc quiescent v cc supply current ? 100 230 v in = 0v or 3.3v i in+ logic ?1? input bias current ? 20 40 v in = 3.3v i in- logic ?0? input bias current ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 7.5 8.6 9.7 threshold v bsuv- v bs supply undervoltage negative going 7.0 8.2 9.4 threshold v ccuv+ v cc supply undervoltage positive going 7.5 8.6 9.7 threshold v ccuv- v cc supply undervoltage negative going 7.0 8.2 9.4 threshold i o+ output high short circuit pulsed current ? 1.0 ? v o = 0v, pw 10 s i o- output low short circuit pulsed current ? 1.0 ? v o = 15v, pw 10 s v a v a static electrical characteristics v bias (v cc , v bs ) = 15v, and t a = 25 c unless otherwise specified. the v in , v th and i in parameters are referenced to com and are applicable to all logic input leads: hin and lin. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v cc = 10v - 20v dynamic electrical characteristics v bias (v cc , v bs ) = 15v, c l = 1000 pf, t a = 25 c unless otherwise specified. figure 1 shows the timing definitions. symbol definition min. typ. max. units test conditions t on turn-on propagation delay ? 80 ? v s = 0v t off turn-off propagation delay ? 60 ? v s = 200v t r turn-on rise time ? 15 25 t f turn-off fall time ? 10 20 dm1 turn-on delay matching | t on (h) - t on (l) | 10 20 30 dm2 turn-off delay matching | t off (h) - t off (l) | 10 20 30 ns
4 www.irf.com IR2011( s ) advance data functional block diagram lead definitions symbol description 8-lead pdip 8-lead soic IR2011 IR2011s part number lead assignments hin logic input for high side gate driver output (ho), in phase lin logic input for low side gate driver output (lo), in phase v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return v b lin uv detect delay v cc uv detect lo v s com s r uv q hin ho level shift circuit low voltage level shift 3v s-trigger 3v s-trigger high voltage buffer low voltage level shift v s v b ho hin com v cc lin lo 1 8 4 5 6 7 3 2 v s v b ho hin com v cc lin lo 1 8 4 5 6 7 3 2
www.irf.com 5 IR2011( s ) advance data figure 1. timing diagram 50% 50% 10% 90% 10% 90% 10% 90% hin / lin ho lo t rise t fall t on (h) t on (l) t off (h) t off (l) dm1 dm2
6 www.irf.com IR2011( s ) advance data data and specifications subject to change without notice. 5/2/2003 01-6014 01-3003 01 (ms-001ab) 8-lead pdip case outlines 01-6027 01-0021 11 (ms-012aa) 8-lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & toleranc ing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions no t to exc eed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions no t to exc eed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic
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